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[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4806 | Author: 张雷 | Hits:

[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 56068 | Author: 地方 | Hits:

[Other resource] VerilogHDLTestBenchPrimer

Description: 讲解Verilog 的testbench的书写方法。-on Verilog testbench writing.
Platform: | Size: 58083 | Author: CGT | Hits:

[File Operate] verilog_testbench_preliminary

Description: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Platform: | Size: 60969 | Author: 刘彦 | Hits:

[Other resource] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench
Platform: | Size: 1169 | Author: QU YIFAN | Hits:

[Other resource] verilog

Description: 一个简单状态机的.v文件，含testbench
Platform: | Size: 1141 | Author: QU YIFAN | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] flash接口控制_verilog

Description: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Platform: | Size: 870400 | Author: 李楠 | Hits:

[VHDL-FPGA-Verilog] wavegenerator_testbench

Description: 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
Platform: | Size: 4096 | Author: liu | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Other] testbench_teach

Description: 关于数字电路设计仿真设计的仿真设计文件的编写教程-on digital circuit design simulation design of the simulation design documents prepared Directory
Platform: | Size: 90112 | Author: | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1024 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[VHDL-FPGA-Verilog] hdb3_verilog

Description: modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
Platform: | Size: 22528 | Author: chengroc | Hits:

[VHDL-FPGA-Verilog] VerilogHDLTestBenchPrimer

Description:
Platform: | Size: 58368 | Author: CGT | Hits:

[VHDL-FPGA-Verilog] verilog-testbench-preliminary

Description: 硬件描述语言verilog的testbench的写作方法-the writing method of the testbench of verilog
Platform: | Size: 60416 | Author: 马腾宇 | Hits:

[Industry research] System-verilog-Overview

Description: Verilog overwied. it has writing verilog testbench guidlines
Platform: | Size: 181248 | Author: asad | Hits:

[VHDL-FPGA-Verilog] FIFO_RAM

Description: 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)
Platform: | Size: 3072 | Author: 炜仔mjw | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
Platform: | Size: 14336 | Author: wow111 | Hits:

[VHDL-FPGA-Verilog] Uart-Verilog

Description: verilog实现串口通讯，包括verilog代码和testbench代码(verilog serial communication, including the verilog code and testbench Code)
Platform: | Size: 791552 | Author: 代工 | Hits:
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